1. Field of the Invention
The present invention relates to a fabrication method for a high speed and high packing density semiconductor device. More particularly, the invention relates to a fabrication method for a high speed and high packing density combined semiconductor device (BiCMOS) through the combination of bipolar and complementary metal oxide semiconductors (CMOS), the former being used in high speed circuits, and the latter being used in high packing density circuits.
2. Related Art
Generally, the important points which are taken into account in designing a large-scale integrated circuit are how to increase the operating speed, and how to limit heat radiation in the integrated circuit to a certain level even where the number of elements is greatly increased within the circuit.
In digital circuits, this factor may be expressed by the delay time multiplied by the power of the gate. The smaller this value is, the better the circuit is considered. Generally, bipolar circuits make it possible to lower the time delay in the gate, but their heat radiation is large. Therefore, the number of transistors which can be fabricated within one chip is limited. CMOS circuits make it possible to minimize the heat radiation through the circuit, thereby making them advantageous in terms of power consumption. But due to the limitation in the circuit driving capacity of CMOS transistors, they have the disadvantage that their operating speed is very slow.
And the recent trend in the design of integrated circuits is that the necessity for bipolar analog circuits as well as CMOS digital circuits is increased, because of the requirements for both analog and digital circuits in telecommunications devices.
Accordingly, the technology of combining bipolar devices and CMOS devices within one chip has been developed, and is being used in fields such as telecommunication ICs, and video tape recorder and camera ICs. Recently, the above technology has been applied in gate arrays and memory devices.
These devices are constituted in such a manner than CMOS is used where high packing density is required, while bipolar devices are used where high speed is required, thereby obtaining the functions of high speed, high packing density semiconductor devices.
Prior BiCMOS technology shown in FIG. 1 is fabricated in such a manner that bipolar devices are developed from CMOS devices, and the bipolar devices are fabricated on the basis of the CMOS process technology. Therefore, while the device fabrication for this method is in some ways simple, the high speed which is characteristic of bipolar devices is adversely affected.
In order to overcome this disadvantage, the technology of SBC (standard buried collector) is used as shown in FIG. 2. But in the bipolar devices fabricated by the SBC technology, P-N junction isolation is used for isolation of devices, and the existence of a lateral diffusion and depletion region hinders device area reduction. Furthermore, the resistance and the capacitance of respective devices cannot be further reduced, and therefore improvements in the operating speed of devices cannot be expected.